[DAC] Exploiting Narrow-width Values for Process Variation-tolerant 3D…

SMRL 0 13,723

Joonho Kong, and Sung Woo Chung, "Exploiting Narrow-width Values for Process Variation-tolerant 3D Microprocessors", Design Automation Conference (DAC), San Francisco, CA, June 2012.

 

 

Abstract

Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.

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