[ISLPED] Architecting Large-Scale SRAM Arrays with Monolithic 3D Inte…

SMRL 0 490

Joonho Kong, Young-Ho Gong, and Sung Woo Chung, “Architecting Large-Scale SRAM Arrays with Monolithic 3D Integration”, IEEE/ACM International Symposium on Low Power Electronics Design (ISLPED 2017), Taipei, Taiwan, July 2017.




In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%~1.7% and 49.1%~79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.