[TVLSI] Fine-Grain Voltage Tuned Cache Architecture for Yield Manageme…

SMRL 0 15,970

Joonho Kong, Yan Pan, Serkan Ozdemir, Anitha Mohan, Gokhan Memik, and Sung Woo Chung, "Fine-Grain Voltage Tuned Cache Architecture for Yield Management under Process Variations", IEEE Transactions on VLSI Systems, vol. 20, no. 8, Aug. 2012.


Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.